How To Initialize All Registers Lc3

In the previous post we talked about what emulators and virtual machines are, when they appeared, what is their current status and apply.

What I desire in this set of articles is to explain in a simple and summarized mode how a computer works and the all-time way to do information technology is to create one, I don't mean physically, but rather an emulator. I will explain and write some code throughout the article. To implement the emulator I'll use Rust and the architecture we are going to utilize is from LC-3, since implementing an emulator for x86 is extremely laborious, fifty-fifty for an erstwhile organization.

What is an architecture?🔗

We can say that the architecture of a estimator is a prepare of rules and methods that depict the functionality, system and implementation of a estimator organization.

An excellent case of a computer compages is the von Neumann architecture, which remains the foundation of most computers even today. This architecture was proposed past the brilliant mathematician John von Neumann, the person we tin can dub the uncle of the electronic computer next to his father Alan Turing.

Von Neumann'south architecture proposal for the electronic computer in the year 1945 is equanimous of five main parts, Command Unit (CU), Arithmetics and Logic Unit (ALU), retention, input and output (I/O). In today's computers the command unit and the ALU have merged to become what we know today as the CPU.

What we have been talking nearly so far is what is known as System Design, but when information technology comes to computer architecture, nosotros can also refer to Teaching Set Architecture (ISA) or even a micro-architecture of the computer.

Instruction Set Architecture🔗

An ISA is like a programming language embedded in the CPU that contains and defines data types, registers, means of addressing retentiveness, fundamental functions to facilitate the cosmos of programs every bit well as the I/O model. Some examples of well-known ISAs are x86, MIPS, and ARM. More recently you tin can encounter a growing interest in RISC-V.

As mentioned to a higher place, to meliorate understand how a reckoner works in its genesis nosotros volition use a simplified architecture that has a reduced and uncomplicated ISA, specifically for learning; and then we are going to utilize LC-3. The LC-iii is the perfect candidate because it is used by several universities to teach assembly programming to students and because information technology has a very modest educational activity set compared to x86, only even so, it contains the foundations that a mod CPU also has.

Our Components🔗

As stated above for the creation of our emulator we volition utilize the Rust language, as it is a modern system language and I have a special affection. From at present on, I will make a brief explanation of what we have to do and follow up with lawmaking. At the end of each part I will put a link to GitHub where it contains all the code referring to each part.

It'south fourth dimension to create a project using Cargo and create two main modules. One will be to incorporate our emulator code and the other will comprise the code to interact with the emulator, the communication interface.

Memory🔗

The LC-3 is a sixteen-bit architecture, pregnant that it has 65,536 possible memory locations (we can know this past doing 2^xvi) and each with the capacity to store 16-bit values. This means that our machine will have a total of 128kb of RAM memory. It seems very little compared to modernistic computers, but I guarantee it will exist more than enough for united states to run some interesting programs.

In our code memory will be represented by a simple vector. To minimally organize things, allow'due south create a separate module especially for retention, where later we'll implement some read and write functions.

                      /// Represents the size of a LC-3 memory.                        const                        MEMORY_SIZE            :                        usize = u16::            MAX                        equally usize            ;                                                pub struct                        Retentivity                        {                                                /// Memory is a vector of 65_536 positions                                      cells            :                          [            u16            ; MEMORY_SIZE],                        }

Registers🔗

Registers are an ultra-fast storage category that resides on the CPU itself. This type of storage is accessed in just one CPU cycle, which is extremely fast, equally memory usually takes more than simply one cycle.

Another peculiarity of registers is that they do non accept a memory address, that is, they are not addressable, but rather, affected and accessed through instructions (as nosotros volition see later in this article). A regular CPU task is to do calculations, this is its slap-up function along with decision-making the period of execution. To brand these calculations, the CPU has to use these locations to temporarily shop the values to be used in the operations. Since the number of registers is limited, the CPU is constantly loading values from memory into the registers and at the end of operations put them dorsum into retentiveness.

The LC-3 has a total of ten registers, each exactly 16 bits long. Most are for general utilize, but some have express access to their special functions:

8 general purpose registers (identifying every bit R0-R7)
i register for the program counter (PC)
1 annals with condition flags (COND)

General purpose registers allow you to perform whatever adding that a program needs to run. The program counter is an unsigned integer annals that contains the retention address of the side by side instruction afterward execution. And the status flags are what provide relevant information most the final adding performed.

To represent it in code, let's create a module to correspond a CPU and inside it another i to represent the registers.

                      /// LC-3 CPU condition flags                        #[derive(Default)]                        pub struct                        Flags                        {}                                                /// LC-three CPU registers                        #[derive(Default)]                        pub struct                        Registers                        {                                                /// Full general purpose register 0                                                pub                        r0            :                        u16            ,                                                /// General purpose register 1                                                pub                        r1            :                        u16            ,                                                /// General purpose register 2                                                pub                        r2            :                        u16            ,                                                /// General purpose register 3                                                pub                        r3            :                        u16            ,                                                /// Full general purpose register four                                                pub                        r4            :                        u16            ,                                                /// General purpose register 5                                                pub                        r5            :                        u16            ,                                                /// General purpose register half dozen                                                pub                        r6            :                        u16            ,                                                /// General purpose annals 7                                                pub                        r7            :                        u16            ,                                                /// Program counter                                                pub                        pc            :                        u16            ,                                                // Condition flags                                                pub                        flags            :                          Flags,                        }

To store the state of the CPU registers we volition use a struct, so we will easily see what nosotros alter when implementing each CPU performance. Another observation is that the structure of the flags for now is empty, since we'll talk well-nigh them after.

The derive(Default) directive will automatically implement the default values in the structures, in this example zeroing out all integers and setting booleans to false. This will come in handy later when nosotros have to initialize the structures.

Instructions🔗

Instructions are the commands nosotros can requite to the CPU. These instructions are fundamental operations, that is, they are simple operations like adding between two numbers. Each education is formed by two parts, the opcode that indicates which task has to exist executed and a part with the parameters of the operation, some instructions have no parameters.

We can look at opcodes as a representation of what the CPU "knows how to do". The LC-3 contains a total of 16 opcodes. Everything the calculator can do and all the programs that nosotros will run on it are just sequences of these xvi instructions.

Addition Instruction Structure — Addition Educational activity Structure

The instructions are of stock-still length, always occupying xvi bits long, the kickoff 4 bits are for storing the opcode and the remaining bits are for the parameters.

In a futurity mail we will talk in detail about each of the instructions, what they do and what effects they take on the organisation. There are many ways to implement this part, but the most readable style and for educational purposes we will create an enumeration with all the instructions.

                      //! CPU instructions declaration and  decoder                                                /// LC-iii Instructions                        pub enum                        Instructions                        {                                                /// branch                                      BR            ,                                                /// add together                                      ADD            ,                                                /// load                                      LD            ,                                                /// shop                                      ST            ,                                                /// spring annals                                      JSR            ,                                                /// bitwise and                                      AND            ,                                                /// load register                                      LDR            ,                                                /// store annals                                      STR            ,                                                /// unused                                      RTI            ,                                                /// bitwise not                                      NOT            ,                                                /// load indirect                                      LDI            ,                                                /// store indirect                                      STI            ,                                                /// jump                                      JMP            ,                                                /// reserved (unused)                                      RES            ,                                                /// load effective address                                      LEA            ,                                                /// execute trap                                      TRAP            ,                        }

Note: As we tin see higher up, the LC-3 has a very reduced amount of instructions compared to x86. Other categories of architectures, such as ARM, which follow a RISC philosophy have much less instructions than x86 (CISC), merely there is no fundamental functioning missing. The big divergence between CISC and RISC is that a CISC processor contains multiple circuitous instructions that require more than CPU cycles and facilitate assembly writing, versus simpler and lighter RISC instructions that require more instructions to practice more circuitous operations. Given the higher up, CISC is much more than complex for engineers to design and produce a CPU. In that location is a reason why this has been so and why we are witnessing a shift in CPUs that dominate our everyday lives. Here is a brief only complete explanation of some of the reasons.

Condition Flags🔗

The CPU needs a mode to maintain country of the result of some operations, for example, when at that place is an if x > 0 { … } compare operation. This state can be used by the next instruction to know, in this instance, whether the condition is truthful or simulated. This is how information technology is possible to make conditional jumps.

Each CPU has its variation of condition flags, in the case of the LC-iii there are just 3:

Negative
Zero
Positive

These flags will say the sign of the previous option. To represent them, allow's add new properties to the Flags structure we created earlier.

                      /// LC-three CPU condition flags                        pub struct                        Flags                        {                                                pub                        negative            :                        bool            ,                                                pub                        zilch            :                        bool            ,                                                pub                        positive            :                        bool            ,                        }

Decision🔗

With this we stop creating the base of operations components of our emulator. In the adjacent mail service nosotros will look at some LC-3 associates examples and how to implement some of the instructions. To see all the code implemented in this function please access GitHub.

References🔗

https://www.techopedia.com/definition/26757/computer-compages
https://en.wikipedia.org/wiki/Computer_architecture
https://en.wikipedia.org/wiki/Little_Computer_3
https://en.wikipedia.org/wiki/Processor_register